1. Field of the Invention
The present invention relates to the technique of monitoring events occurring within a processing system, and particularly techniques in which a central processing unit (CPU) within a processing system monitors events within the processing system so as to sequentially coordinate functions being performed within the processing system.
2. State of the Art
In general, a processing or computing system includes several functional system blocks each for performing a certain function or functions within the system. For instance, processing systems often include a data processing unit for processing data loaded into a memory buffer area, a DMA controller for managing direct memory accesses, and/or a memory controller for managing memory accesses between a larger off-chip memory and a smaller on-chip buffer area. Each of these functional elements perform their corresponding functions as instructed by the system""s central processing unit (CPU). Generally, the CPU instructs the functional elements to perform their functions in a particular order so as to implement a given operation with the processing system. For instance, in order to process a block of data, the CPU may 1) initiate a first DMA request that moves a block of data from a first memory area to a second memory, 2) configure a data processing unit into a certain configuration to perform a particular function on the block of data, 3) instruct the configured data processing unit to process the block of data requested in the first DMA request, and 4) initiate a second DMA request to store the processed block of data back to the first memory area. In this example, the above steps have to be performed in a given consecutive order, each being completed prior to starting the next step. For instance, the first step (i.e., the DMA request which moves the data from the first memory area to the second) must be completed prior to the third step (i.e., data processing). In addition, the second step (i.e., configuring the data processing unit) also needs to occur prior to the third step. Finally, all of steps 1)-3) need to be completed prior to the fourth step (i.e., storing the processed data back into the first memory).
In the past, in order to let the CPU know when a given event, function, or step (as described above) is completed so that the CPU can initiate a next step of an operation, the functional element which had just completed its function interrupts the CPU by transmitting an interrupt signal on the system bus to the CPU. The CPU then stops what it is currently operating on and services the interrupt signal by performing some function that is related to the event that initiated the interrupt. For instance, if a data processing unit finishes processing a block of data, the data processing unit would generate an interrupt to notify the CPU that it is done. The CPU, in turn, interrupts its normal processing sequence to determine what should be done to service the interrupt. The disadvantage of this technique is that interrupts and the associated steps following interrupts generate traffic on the system bus thereby tying up the system bus as well as tying up the CPU.
The objective of the present invention is to avoid the overhead caused when servicing interrupts and in general to provide a manner in which to monitor events within a processing system without using interrupts and without tying up the system bus.
The present invention is a system and method in which events occurring in a processing system are monitored using logic flags that are stored in logic flag registers. The logic flag registers reside within the functional system blocks in which the events are occurring. As the events occur, the functional system blocks update their logic flag registers. The CPU in the processing system is directly coupled on dedicated signal lines to the logic flag registers allowing the CPU to constantly monitor the state of the flags and to avoid using the system bus of the processing system. In one embodiment, the CPU continuously performs an algorithm loop which reads the flags, until it detects that the state of the flag has changed indicating that the status of the event. The CPU can monitor all flags or only certain flags during specified times.